Intel teases next-gen GPUs built to power record-breaking new supercomputers

Intel has teased a new line of server GPUs built to power the next generation of record-breaking supercomputers, codenamed Rialto Bridge.

An evolution of the existing Ponte Vecchio design, the new cards will feature as many as 160 Xe GPU cores and “offer significantly increased density, performance and efficiency”, the company says.

Intel has remained tight-lipped about the broader specification and potential performance gains, but did reveal Rialto Bridge GPUs are expected to begin sampling by mid-2023.

Intel in the HPC market

The high performance computing (HPC) market has long been of great strategic importance to Intel. However, despite the historic dominance of its Xeon server processors in the space, there is evidence to suggest the company’s lead is slipping.

Only one of the world’s top ten most powerful supercomputers are now powered by Intel, according to the latest Top500 rankings, with AMD and Arm-based chips scrapping it out at the top. And AMD is making inroads further down the list, too.

In an effort to broaden its presence in the HPC market, Intel unveiled its first ever dedicated data center GPU, Ponte Vecchio, in 2021. The card is set to feature in the upcoming Aurora supercomputer later this year and apparently delivers significant performance gains across financial services and other workloads.

Rialto Bridge GPUs will be built around the same architecture as Ponte Vecchio, but benefit from the company’s next-generation process technology (that’s as specific as Intel is willing to be at this point) and increased I/O bandwidth.

The launch has been characterized by Intel as the next step on the “sprint” towards the zettascale era, which will bring supercomputing systems 1,000x more powerful than the most performant machines today.

“We have an aggressive HPC roadmap planned through 2024 that will deliver a diverse portfolio of heterogeneous architectures,” said Jeff McVeight, VP & GM of the Intel Super Compute Group.

“These architectures will allow us to improve performance by orders of magnitude while reducing power demands across both general-purpose and emerging workloads such as AI, encryption and analytics.”

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